SPI.h

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#ifndef HARDWARE_AVR_SPI_H
#define HARDWARE_AVR_SPI_H

#include "GPIO.h"
#include "SPI.h"

namespace Hardware {

#if defined(SPDR)
class SPI : public ::SPI {
public:
  SPI() :
    ::SPI()
  {
    m_ss.output();
    m_sck.output();
    m_mosi.output();
    m_miso.input();
  }

  virtual uint8_t prescale(uint32_t frequency)
  {
    uint16_t scale = F_CPU / frequency;
    if (scale <= 2)  return (0b100);
    if (scale <= 4)  return (0b000);
    if (scale <= 8)  return (0b101);
    if (scale <= 16) return (0b001);
    if (scale <= 32) return (0b110);
    if (scale <= 64) return (0b111);
    return (0b011);
  }

  virtual void acquire(uint8_t mode, uint8_t bitorder, uint8_t prescale)
  {
    // Wait for bus manager to be released
    lock();

    // Set control registers: mode, bitorder and clock
    SPCR = _BV(SPE)
         | _BV(MSTR)
         | (bitorder == LSBFIRST ? _BV(DORD) : 0)
         | ((mode & 0x03) << CPHA)
         | (prescale & 0x03);
    SPSR = ((prescale >> 2) & 0x01);
  }

  virtual uint8_t transfer(uint8_t value)
    __attribute__((always_inline))
  {
    SPDR = value;
    __asm__ __volatile__("nop" ::: "memory");
    loop_until_bit_is_set(SPSR, SPIF);
    return (SPDR);
  }

  virtual void transfer(void* dest, const void* src, size_t count)
  {
    if (count == 0 || dest == NULL || src == NULL) return;
    const uint8_t* sp = (const uint8_t*) src;
    uint8_t* dp = (uint8_t*) dest;
    uint8_t value = *sp++;
    SPDR = value;
    while (--count) {
      value = *sp++;
      __asm__ __volatile__("" ::: "memory");
      loop_until_bit_is_set(SPSR, SPIF);
      SPDR = value;
      __asm__ __volatile__("" ::: "memory");
      *dp++ = SPDR;
    }
    loop_until_bit_is_set(SPSR, SPIF);
    *dp = SPDR;
  }

  virtual void read(void* buf, size_t count)
  {
    if (count == 0 || buf == NULL) return;
    uint8_t* bp = (uint8_t*) buf;
    SPDR = 0;
    while (--count) {
      __asm__ __volatile__("nop" ::: "memory");
      loop_until_bit_is_set(SPSR, SPIF);
      SPDR = 0;
      __asm__ __volatile__("" ::: "memory");
      *bp++ = SPDR;
    }
    loop_until_bit_is_set(SPSR, SPIF);
    *bp = SPDR;
  }

  virtual void write(const void* buf, size_t count)
  {
    if (count == 0 || buf == NULL) return;
    uint8_t* bp = (uint8_t*) buf;
    uint8_t value = *bp++;
    SPDR = value;
    while (--count) {
      value = *bp++;
      __asm__ __volatile__("" ::: "memory");
      loop_until_bit_is_set(SPSR, SPIF);
      SPDR = value;
      __asm__ __volatile__("" ::: "memory");
    }
    loop_until_bit_is_set(SPSR, SPIF);
  }

protected:
  GPIO<BOARD::SS> m_ss;

  GPIO<BOARD::SCK> m_sck;

  GPIO<BOARD::MOSI> m_mosi;

  GPIO<BOARD::MISO> m_miso;
};

#elif defined(USIDR)

class SPI : public ::SPI {
public:
  SPI() :
    ::SPI()
  {
    m_ss.output();
    m_sck.output();
    m_mosi.output();
    m_miso.input();
  }

  virtual void acquire(uint8_t mode, uint8_t bitorder, uint8_t prescale)
  {
    // Wait for bus manager to be released
    lock();

    // Not used: only MSBFIRST bitorder and max frequency
    (void) bitorder;
    (void) prescale;

    // Set clock polarity
    m_sck.write(mode & 0x02);

    // Cache clocking command
    m_usicr = (_BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC));
    if (mode == 1 || mode == 2) m_usicr |= _BV(USICS0);
  }

  virtual uint8_t transfer(uint8_t value)
  {
    USIDR = value;
    USISR = _BV(USIOIF);
    register uint8_t cntl = m_usicr;
    do {
      USICR = cntl;
    } while ((USISR & _BV(USIOIF)) == 0);
    return (USIDR);
  }

protected:
  GPIO<BOARD::SS> m_ss;

  GPIO<BOARD::SCK> m_sck;

  GPIO<BOARD::MOSI> m_mosi;

  GPIO<BOARD::MISO> m_miso;

  uint8_t m_usicr;
};
#endif

};
#endif