TWI.h

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#ifndef HARDWARE_AVR_TWI_H
#define HARDWARE_AVR_TWI_H

#include "TWI.h"

namespace Hardware {
class TWI : public ::TWI {
public:
  TWI(uint32_t freq = DEFAULT_FREQ)
  {
    // Initiate hardware registers: baudrate and control
    TWBR = ((F_CPU / freq) - 16) / 2;
    TWSR = 0;
    TWCR = 0;
  }

  virtual bool acquire()
  {
    // Acquire bus and issue start condition
    lock();
    m_start = true;
    TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWSTA);
    return iowait(START);
  }

  virtual bool release()
  {
    // Mark bus manager as idle
    m_start = false;
    unlock();

    // Issue stop condition and release bus
    TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWSTO);

    // Allow the command to complete
    delayMicroseconds(10);
    return (true);
  }

  virtual int read(uint8_t addr, void* buf, size_t count)
  {
    // Check if repeated start condition should be generated
    if (!m_start) {
      TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWSTA);
      if (!iowait(REP_START)) return (false);
    }
    m_start = false;

    // Address device with read request and check that it acknowledges
    TWDR = addr | 0x01;
    TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWEA);
    if (!iowait(MR_SLA_ACK)) return (-1);

    // Read bytes and acknowledge until required size
    uint8_t* bp = (uint8_t*) buf;
    size_t size = count;
    while (size--) {
      if (size != 0) {
        TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWEA);
        if (!iowait(MR_DATA_ACK)) return (-1);
      }
      else {
        TWCR = _BV(TWEN) | _BV(TWINT);
        if (!iowait(MR_DATA_NACK)) return (-1);
      }
      *bp++ = TWDR;
    }
    return (count);
  }

  virtual int write(uint8_t addr, iovec_t* vp)
  {
    // Check if repeated start condition should be generated
    if (!m_start) {
      TWCR = _BV(TWEN) | _BV(TWINT) | _BV(TWSTA);
      if (!iowait(REP_START)) return (-1);
    }
    m_start = false;

    // Address device with write request and check that it acknowledges
    TWDR = addr | 0x00;
    TWCR = _BV(TWEN) | _BV(TWINT);
    if (!iowait(MT_SLA_ACK)) return (-1);
    if (vp == NULL) return (0);

    // Write given io vector buffers to device
    int count = 0;
    for(; vp->buf != NULL; vp++) {
      const uint8_t* bp = (const uint8_t*) vp->buf;
      size_t size = vp->size;
      count += size;
      while (size--) {
        TWDR = *bp++;
        TWCR = _BV(TWEN) | _BV(TWINT);
        if (!iowait(MT_DATA_ACK)) return (-1);
      }
    }
    return (count);
  }

protected:
  enum {
    START = 0x08,               
    REP_START = 0x10,           
    ARB_LOST = 0x38,            
    MT_SLA_ACK = 0x18,          
    MT_SLA_NACK = 0x20,         
    MT_DATA_ACK = 0x28,         
    MT_DATA_NACK = 0x30,        
    MR_SLA_ACK = 0x40,          
    MR_SLA_NACK = 0x48,         
    MR_DATA_ACK = 0x50,         
    MR_DATA_NACK = 0x58,        
    MASK = 0xF8,                
    BUS_ERROR = 0x00            
  } __attribute__((packed));


  bool iowait(uint8_t status)
  {
    loop_until_bit_is_set(TWCR, TWINT);
    return ((TWSR & MASK) == status);
  }

  bool m_start;
};
};

#endif