SPI.hh

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#ifndef COSA_SPI_HH
#define COSA_SPI_HH

#include "Cosa/Types.h"
#include "Cosa/Bits.h"
#include "Cosa/OutputPin.hh"
#include "Cosa/Interrupt.hh"
#include "Cosa/Event.hh"
#include "Cosa/IOStream.hh"

class SPI {
public:
  enum Clock {
    DIV2_CLOCK = 0x04,          
    DIV4_CLOCK = 0x00,          
    DIV8_CLOCK = 0x05,          
    DIV16_CLOCK = 0x01,         
    DIV32_CLOCK = 0x06,         
    DIV64_CLOCK = 0x02,         
    DIV128_CLOCK = 0x03,        
    DEFAULT_CLOCK = DIV4_CLOCK  
  } __attribute__((packed));

  enum Order {
    MSB_ORDER = 0,              
    LSB_ORDER = 1,              
    DEFAULT_ORDER = MSB_ORDER   
  } __attribute__((packed));

  enum Pulse {
    ACTIVE_LOW = 0,             
    ACTIVE_HIGH = 1,            
    PULSE_LOW = 2,              
    PULSE_HIGH = 3,             
    DEFAULT_PULSE = ACTIVE_LOW  
  } __attribute__((packed));

  class Driver {
  public:
    Driver(Board::DigitalPin cs,
           Pulse pulse = DEFAULT_PULSE,
           Clock rate = DEFAULT_CLOCK,
           uint8_t mode = 0,
           Order order = MSB_ORDER,
           Interrupt::Handler* irq = NULL);

    static Clock clock(uint32_t freq)
      __attribute__((always_inline))
    {
      if (freq >= (F_CPU / 2)) return (SPI::DIV2_CLOCK);
      if (freq >= (F_CPU / 4)) return (SPI::DIV4_CLOCK);
      if (freq >= (F_CPU / 8)) return (SPI::DIV8_CLOCK);
      if (freq >= (F_CPU / 16)) return (SPI::DIV16_CLOCK);
      if (freq >= (F_CPU / 32)) return (SPI::DIV32_CLOCK);
      if (freq >= (F_CPU / 64)) return (SPI::DIV64_CLOCK);
      return (SPI::DIV128_CLOCK);
    }

    static Clock cycle(uint16_t ns)
      __attribute__((always_inline))
    {
      if (ns <= (1000000L / (F_CPU/2000L))) return (SPI::DIV2_CLOCK);
      if (ns <= (1000000L / (F_CPU/4000L))) return (SPI::DIV4_CLOCK);
      if (ns <= (1000000L / (F_CPU/8000L))) return (SPI::DIV8_CLOCK);
      if (ns <= (1000000L / (F_CPU/16000L))) return (SPI::DIV16_CLOCK);
      if (ns <= (1000000L / (F_CPU/32000L))) return (SPI::DIV32_CLOCK);
      if (ns <= (1000000L / (F_CPU/64000L))) return (SPI::DIV64_CLOCK);
      return (SPI::DIV128_CLOCK);
    }

    void set_clock(Clock rate);

    void set_clock(uint32_t freq)
      __attribute__((always_inline))
    {
      set_clock(clock(freq));
    }

  protected:
    Driver* m_next;             
    Interrupt::Handler* m_irq;  
    OutputPin m_cs;             
    Pulse m_pulse;              
#if defined(USICR)
    const uint8_t m_cpol;       
    uint8_t m_usicr;            
    uint8_t m_data;             
#else
    uint8_t m_spcr;             
    uint8_t m_spsr;             
#endif
    friend class SPI;
  };

  SPI();

  bool attach(Driver* dev);

  void acquire(Driver* dev);

  void release();

  void begin()
    __attribute__((always_inline))
  {
    if (m_dev->m_pulse < PULSE_LOW) m_dev->m_cs.toggle();
  }

  void end()
    __attribute__((always_inline))
  {
    m_dev->m_cs.toggle();
    if (m_dev->m_pulse > ACTIVE_HIGH) m_dev->m_cs.toggle();
  }

#if defined(USIDR)

  uint8_t transfer(uint8_t data)
    __attribute__((always_inline))
  {
    USIDR = data;
    USISR = _BV(USIOIF);
    register uint8_t cntl = m_dev->m_usicr;
    do {
      USICR = cntl;
    } while ((USISR & _BV(USIOIF)) == 0);
    return (USIDR);
  }

  void transfer_start(uint8_t data)
    __attribute__((always_inline))
  {
    m_dev->m_data = data;
  }

  uint8_t transfer_await()
    __attribute__((always_inline))
  {
    return (transfer(m_dev->m_data));
  }

  uint8_t transfer_next(uint8_t data)
    __attribute__((always_inline))
  {
    uint8_t res = transfer_await();
    transfer_start(data);
    return (res);
  }

  static void powerup()
  {
    power_usi_enable();
  }

  static void powerdown()
  {
    power_usi_disable();
  }
#else

  uint8_t transfer(uint8_t data)
    __attribute__((always_inline))
  {
    SPDR = data;
    loop_until_bit_is_set(SPSR, SPIF);
    return (SPDR);
  }

  void transfer_start(uint8_t data)
    __attribute__((always_inline))
  {
    SPDR = data;
  }

  uint8_t transfer_await()
    __attribute__((always_inline))
  {
    loop_until_bit_is_set(SPSR, SPIF);
    return (SPDR);
  }

  uint8_t transfer_next(uint8_t data)
    __attribute__((always_inline))
  {
    loop_until_bit_is_set(SPSR, SPIF);
    uint8_t res = SPDR;
    SPDR = data;
    return (res);
  }

  static void powerup()
  {
    power_spi_enable();
  }

  static void powerdown()
  {
    power_spi_disable();
  }
#endif

  void transfer(void* buf, size_t count);

  void transfer(void* dst, const void* src, size_t count);

  void read(void* buf, size_t count);

  void write(const void* buf, size_t count);

  void write_P(const void* buf, size_t count);

  void write(const iovec_t* vec)
    __attribute__((always_inline))
  {
    for (const iovec_t* vp = vec; vp->buf != NULL; vp++)
      write(vp->buf, vp->size);
  }

private:
  Driver* m_list;               
  Driver* m_dev;                
  volatile bool m_busy;         
};

extern SPI spi;

IOStream& operator<<(IOStream& outs, SPI::Clock rate);

#endif