TWI.hh

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#ifndef COSA_TWI_HH
#define COSA_TWI_HH

#include "Cosa/Types.h"
#if defined(BOARD_ATTINY)
#include "Cosa/USI/TWI.hh"
#else
#include "Cosa/Event.hh"
#include <avr/power.h>

class TWI {
public:
  static const uint32_t DEFAULT_FREQ = 100000L;

  static const uint32_t MAX_FREQ = (F_CPU / (16 + 2*2));

  class Driver {
  public:
   Driver(uint8_t addr) :
     m_addr(addr << 1),
     m_async(false)
    {}

    bool is_async() const
    {
      return (m_async);
    }

    void sync_request()
    {
      m_async = false;
    }

    void async_request()
    {
      m_async = true;
    }

    virtual void on_completion(uint8_t type, int count)
    {
      UNUSED(type);
      UNUSED(count);
    }

  protected:
    uint8_t m_addr;

    bool m_async;

    friend class TWI;
    friend void TWI_vect(void);
  };

  class Slave : public Driver, public Event::Handler {
  public:
    Slave(uint8_t addr) : Driver(addr), Event::Handler() {}

    void read_buf(void* buf, size_t size);

    void write_buf(void* buf, size_t size);

    void begin();

    virtual void on_completion(uint8_t type, int count)
    {
      Event::push(type, this, count);
    }

    virtual void on_request(void* buf, size_t size) = 0;

  protected:
    static const uint8_t WRITE_IX = 0;
    static const uint8_t READ_IX = 1;

    virtual void on_event(uint8_t type, uint16_t value);

    friend class TWI;
    friend void TWI_vect(void);
  };

  TWI() :
    m_state(IDLE_STATE),
    m_status(NO_INFO),
    m_ix(0),
    m_next(NULL),
    m_last(NULL),
    m_count(0),
    m_dev(NULL),
    m_freq(((F_CPU / DEFAULT_FREQ) - 16) / 2),
    m_busy(false)
  {
    for (uint8_t ix = 0; ix < VEC_MAX; ix++) {
      m_vec[ix].buf = 0;
      m_vec[ix].size = 0;
    }
  }

  void acquire(TWI::Driver* dev);

  void release();

  bool write_request(void* buf, size_t size);

  bool write_request(uint8_t header, void* buf, size_t size);

  bool write_request(uint16_t header, void* buf, size_t size);

  bool read_request(void* buf, size_t size);

  int write(void* buf, size_t size)
    __attribute__((always_inline))
  {
    if (UNLIKELY(!write_request(buf, size))) return (EIO);
    return (await_completed());
  }

  int write(uint8_t header, void* buf = 0, size_t size = 0)
    __attribute__((always_inline))
  {
    if (UNLIKELY(!write_request(header, buf, size))) return (EIO);
    return (await_completed());
  }

  int write(uint16_t header, void* buf = 0, size_t size = 0)
    __attribute__((always_inline))
  {
    if (UNLIKELY(!write_request(header, buf, size))) return (EIO);
    return (await_completed());
  }

  int read(void* buf, size_t size)
    __attribute__((always_inline))
  {
    if (UNLIKELY(!read_request(buf, size))) return (EIO);
    return (await_completed());
  }

  int await_completed();

  void set_freq(uint32_t hz)
    __attribute__((always_inline))
  {
    m_freq = (hz < MAX_FREQ) ? (((F_CPU / hz) - 16) / 2) : 2;
  }

  void powerup()
  {
    power_twi_enable();
  }

  void powerdown()
  {
    power_twi_disable();
  }

private:
  enum State {
    ERROR_STATE,                
    IDLE_STATE,                 
    MT_STATE,                   
    MR_STATE,                   
    ST_STATE,                   
    SR_STATE                    
  } __attribute__((packed));

# define TWI_STATUS(x) ((x) >> 3)

  enum {
    START = TWI_STATUS(0x08),
    REP_START = TWI_STATUS(0x10),
    ARB_LOST = TWI_STATUS(0x38),

    MT_SLA_ACK = TWI_STATUS(0x18),
    MT_SLA_NACK = TWI_STATUS(0x20),
    MT_DATA_ACK = TWI_STATUS(0x28),
    MT_DATA_NACK = TWI_STATUS(0x30),

    MR_SLA_ACK = TWI_STATUS(0x40),
    MR_SLA_NACK = TWI_STATUS(0x48),
    MR_DATA_ACK = TWI_STATUS(0x50),
    MR_DATA_NACK = TWI_STATUS(0x58),

    ST_SLA_ACK = TWI_STATUS(0xA8),
    ST_ARB_LOST_SLA_ACK = TWI_STATUS(0xB0),
    ST_DATA_ACK = TWI_STATUS(0xB8),
    ST_DATA_NACK = TWI_STATUS(0xC0),
    ST_LAST_DATA = TWI_STATUS(0xC8),

    SR_SLA_ACK = TWI_STATUS(0x60),
    SR_ARB_LOST_SLA_ACK = TWI_STATUS(0x68),
    SR_GCALL_ACK = TWI_STATUS(0x70),
    SR_ARB_LOST_GCALL_ACK = TWI_STATUS(0x78),
    SR_DATA_ACK = TWI_STATUS(0x80),
    SR_DATA_NACK = TWI_STATUS(0x88),
    SR_GCALL_DATA_ACK = TWI_STATUS(0x90),
    SR_GCALL_DATA_NACK = TWI_STATUS(0x98),
    SR_STOP = TWI_STATUS(0xA0),

    NO_INFO = TWI_STATUS(0xF8),
    BUS_ERROR = TWI_STATUS(0x00)
  } __attribute__((packed));

  enum {
    WRITE_OP = 0x00,            
    READ_OP = 0x01,             
    ADDR_MASK = 0xfe            
  } __attribute__((packed));

  static const uint8_t NEXT_IX = 255;

  enum Command {
    NULL_CMD = 0,
    IDLE_CMD = _BV(TWEA) | _BV(TWEN) | _BV(TWIE),
    START_CMD = _BV(TWINT) | _BV(TWEA) | _BV(TWSTA) | _BV(TWEN) | _BV(TWIE),
    DATA_CMD = _BV(TWINT) | _BV(TWEN) | _BV(TWIE),
    ACK_CMD =  _BV(TWINT) | _BV(TWEA) | _BV(TWEN) | _BV(TWIE),
    NACK_CMD = _BV(TWINT) | _BV(TWEN) | _BV(TWIE),
    STOP_CMD =  _BV(TWINT) | _BV(TWEA) | _BV(TWSTO) | _BV(TWEN) | _BV(TWIE)
  } __attribute__((packed));

  static const uint8_t HEADER_MAX = 4;
  static const uint8_t VEC_MAX = 4;
  uint8_t m_header[HEADER_MAX];
  iovec_t m_vec[VEC_MAX];
  volatile State m_state;
  volatile uint8_t m_status;
  volatile uint8_t m_ix;
  volatile uint8_t* m_next;
  volatile uint8_t* m_last;
  volatile int m_count;
  uint8_t m_addr;
  Driver* m_dev;
  uint8_t m_freq;
  volatile bool m_busy;

  void isr_start(State state, uint8_t ix);

  bool isr_write(Command cmd);

  bool isr_read(Command cmd = NULL_CMD);

  void isr_stop(State state, uint8_t type = Event::NULL_TYPE);

  bool request(uint8_t op);

  friend void TWI_vect(void);
};
#endif

extern TWI twi;
#endif