template<uint8_t N>
class Soft::SRPO< N >
Soft N-Shift Register Parallel Output, 2-pin. The shift registers (74HC164/74HC595) may be cascaded for N*8-bit parallel output port (see circuit below). The pins are numbered from the first connect shift register (Q0..Q7) and updwards in the chain (Q8..Q15) and so on.
Circuit
74HC164 (VCC)
+----U----+ |
(D3/SDA)----------+-1-|DSA VCC|-14-+
+-2-|DSB Q7|-13------------(Q7)--+
(Q0)----------------3-|Q0 Q6|-12------------(Q6) |
(Q1)----------------4-|Q1 Q5|-11------------(Q5) |
(Q2)----------------5-|Q2 Q4|-10------------(Q4) |
(Q3)----------------6-|Q3 /MR|--9-----------(VCC) |
+-7-|GND CP|--8--------(SCL/D4)--)-+
| +---------+ | |
| 0.1uF | |
(GND)-----||-------(VCC) | |
| |
+-----------------------------------+ |
| |
| 74HC164 (VCC) |
| +----U----+ | |
+-1-|DSA VCC|-14-+ |
+-2-|DSB Q7|-13-----------(Q15)--+ |
(Q8)----------------3-|Q0 Q6|-12-----------(Q14) | |
(Q9)----------------4-|Q1 Q5|-11-----------(Q13) | |
(Q10)---------------5-|Q2 Q4|-10-----------(Q12) | |
(Q11)---------------6-|Q3 /MR|--9-----------(VCC) | |
+-7-|GND CP|--8------------------)-+
| +---------+ | |
| 0.1uF | |
(GND)-----||-------(VCC) v v
- Parameters
-
[in] | N | number of shift registers (N * 8 output pins). |
Definition at line 69 of file SRPO.hh.