22 #if defined(BOARD_ATTINY) 25 #if defined(USE_FAST_MODE) 27 #define T2 ((((I_CPU * 1300) / 10000) + 1) / 4) 28 #define T4 ((((I_CPU * 600) / 10000) + 1) / 4) 31 #define T2 ((((I_CPU * 4700) / 10000) + 1) / 4) 32 #define T4 ((((I_CPU * 4000) / 10000) + 1) / 4) 35 TWI twi __attribute__ ((weak));
57 USICR = TWI::CR_START_MODE;
58 USISR = TWI::SR_CLEAR_ALL;
64 if (
twi.state() != TWI::IDLE)
return;
66 USICR = TWI::CR_TRANSFER_MODE;
67 USISR = TWI::SR_CLEAR_ALL;
68 twi.state(TWI::START_CHECK);
73 switch (
twi.state()) {
77 case TWI::START_CHECK:
80 if ((addr & TWI::ADDR_MASK) !=
twi.m_dev->
m_addr)
goto restart;
81 if (addr & TWI::READ_OP) {
82 twi.state(TWI::READ_REQUEST);
83 twi.buf(TWI::READ_IX);
86 twi.state(TWI::WRITE_REQUEST);
87 twi.buf(TWI::WRITE_IX);
91 USISR = TWI::SR_CLEAR_ACK;
99 if (USIDR)
goto restart;
101 case TWI::READ_REQUEST:
104 if (!
twi.get(data))
goto restart;
107 USISR = TWI::SR_CLEAR_DATA;
108 twi.state(TWI::READ_COMPLETED);
112 case TWI::READ_COMPLETED:
115 USISR = TWI::SR_CLEAR_ACK;
116 twi.state(TWI::ACK_CHECK);
122 case TWI::WRITE_REQUEST:
124 USISR = TWI::SR_CLEAR_DATA;
125 twi.state(TWI::WRITE_COMPLETED);
127 if (USISR & _BV(USIPF)) {
128 USICR = TWI::CR_SERVICE_MODE;
129 USISR = TWI::SR_CLEAR_ALL;
131 twi.state(TWI::SERVICE_REQUEST);
135 case TWI::WRITE_COMPLETED:
137 uint8_t data = USIDR;
138 USIDR = (
twi.put(data) ? 0x00 : 0x80);
140 USISR = TWI::SR_CLEAR_ACK;
141 twi.state(TWI::WRITE_REQUEST);
148 USICR = TWI::CR_START_MODE;
149 USISR = TWI::SR_CLEAR_DATA;
150 twi.state(TWI::IDLE);
163 USICR = TWI::CR_START_MODE;
164 USISR = TWI::SR_CLEAR_DATA;
178 for (uint8_t ix = 0; ix < VEC_MAX; ix++) {
189 while (!m_scl.is_set())
200 return ((USISR & _BV(USISIF)) != 0);
204 TWI::transfer(uint8_t data, uint8_t bits)
207 uint8_t SR = SR_CLEAR_ALL;
208 if (bits == 1) SR |= (0x0E << USICNT0);
215 USICR = CR_DATA_MODE;
216 while (!m_scl.is_set())
219 USICR = CR_DATA_MODE;
220 }
while (!(USISR & _BV(USIOIF)));
236 while (!m_scl.is_set())
243 return ((USISR & _BV(USIPF)) != 0);
247 TWI::request(uint8_t op)
249 bool is_read = (op & READ_OP);
250 uint8_t* next = (uint8_t*) m_vec[0].buf;
251 uint8_t* last = next + m_vec[0].
size;
255 if (!start())
return (
EFAULT);
257 transfer(m_dev->
m_addr | is_read);
259 if (transfer(0, 1))
goto nack;
262 for (uint8_t ix = 1; next != 0; ix++) {
263 while (next != last) {
267 *next++ = transfer(0);
268 transfer((next != last) ? 0x00 : 0xff, 1);
274 if (transfer(0, 1))
goto nack;
277 next = (uint8_t*) m_vec[ix].buf;
278 last = next + m_vec[ix].
size;
282 if (!stop())
return (
EFAULT);
290 uint8_t key =
lock(m_busy);
300 USICR = CR_INIT_MODE;
301 USISR = SR_CLEAR_ALL;
329 return (request(WRITE_OP));
333 TWI::write(uint8_t header,
void* buf,
size_t size)
336 m_header[0] = header;
340 return (request(WRITE_OP));
344 TWI::write(uint16_t header,
void* buf,
size_t size)
347 m_header[0] = (header >> 8);
348 m_header[1] = header;
352 return (request(WRITE_OP));
361 return (request(READ_OP));
void USI_START_vect(void)
static const uint8_t READ_IX
virtual void on_event(uint8_t type, uint16_t value)
void write_buf(void *buf, size_t size)
virtual void on_request(void *buf, size_t size)=0
size_t size
Size of buffer in bytes.
int read(void *buf, size_t size)
void * buf
Buffer pointer.
void read_buf(void *buf, size_t size)
int write(void *buf, size_t size)
void acquire(TWI::Driver *dev)
static const uint8_t WRITE_IX
virtual void on_completion(uint8_t type, int count)
void iovec_arg(iovec_t *&vp, const void *buf, size_t size)
void iovec_end(iovec_t *&vp)