21 #ifndef COSA_SOFT_SPI_HH 22 #define COSA_SOFT_SPI_HH 49 } __attribute__((packed));
56 } __attribute__((packed));
65 } __attribute__((packed));
98 __attribute__((always_inline))
116 __attribute__((always_inline))
138 __attribute__((always_inline))
217 __attribute__((always_inline))
219 if (m_dev->m_pulse <
PULSE_LOW) m_dev->m_cs.toggle();
227 __attribute__((always_inline))
229 m_dev->m_cs.toggle();
230 if (m_dev->m_pulse >
ACTIVE_HIGH) m_dev->m_cs.toggle();
239 __attribute__((always_inline))
241 m_dev->m_data = data;
250 __attribute__((always_inline))
262 __attribute__((always_inline))
284 void transfer(
void* buf,
size_t count);
294 void transfer(
void* dst,
const void* src,
size_t count)
297 uint8_t* dp = (uint8_t*) dst;
298 const uint8_t* sp = (
const uint8_t*) src;
299 do *dp++ =
transfer(*sp++);
while (--count);
308 void read(
void* buf,
size_t count)
311 uint8_t* bp = (uint8_t*) buf;
312 do *bp++ =
transfer(0x00);
while (--count);
321 void write(
const void* buf,
size_t count)
324 const uint8_t* bp = (
const uint8_t*) buf;
325 do transfer(*bp++);
while (--count);
334 void write_P(
const uint8_t* buf,
size_t count)
337 do transfer(pgm_read_byte(buf++));
while (--count);
346 __attribute__((always_inline))
349 write(vp->buf, vp->size);
354 volatile bool m_busy;
Pulse high on end of transaction.
uint8_t transfer(uint8_t data)
static Clock clock(uint32_t freq)
Least significant bit first.
void write(const iovec_t *vec)
Divide system clock by 128.
Driver(Board::DigitalPin cs, Pulse pulse=DEFAULT_PULSE, Clock clock=DEFAULT_CLOCK, uint8_t mode=0, Order order=MSB_ORDER, Interrupt::Handler *irq=NULL)
void acquire(Driver *dev)
Divide system clock by 8.
Divide system clock by 64.
void read(void *buf, size_t count)
static Clock cycle(uint16_t ns)
uint8_t transfer_next(uint8_t data)
Active low logic during transaction.
void set_clock(uint32_t freq)
void transfer(void *dst, const void *src, size_t count)
Divide system clock by 16.
void write(const void *buf, size_t count)
void * buf
Buffer pointer.
Active high logic during transaction.
Divide system clock by 32.
Pulse m_pulse
Chip select pulse mode.
uint8_t m_mode
Mode for phase and transition.
Pulse low on end of transaction.
void transfer_start(uint8_t data)
OutputPin m_cs
Device chip select pin.
void write_P(const uint8_t *buf, size_t count)
Driver * m_next
List of drivers.
Most significant bit first.
Divide system clock by 2.
Interrupt::Handler * m_irq
Interrupt handler.
Order m_order
Data direction; bit order.
SPI(Board::DigitalPin miso, Board::DigitalPin mosi, Board::DigitalPin sck)
Divide system clock by 4.
uint8_t m_data
Data to transfer.
void set_clock(Clock rate)