NRF24L01P.hh

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#ifndef COSA_NRF24L01P_HH
#define COSA_NRF24L01P_HH

#include "Cosa/SPI.hh"
#include "Cosa/OutputPin.hh"
#include "Cosa/ExternalInterrupt.hh"
#include "Cosa/Wireless.hh"
#if !defined(BOARD_ATTINYX5)

class NRF24L01P : protected SPI::Driver, public Wireless::Driver {
public:
  static const size_t DEVICE_PAYLOAD_MAX = 32;

  static const size_t PAYLOAD_MAX = DEVICE_PAYLOAD_MAX - 2;

#if defined(BOARD_ATTINYX4)
  NRF24L01P(uint16_t net, uint8_t dev,
            Board::DigitalPin csn = Board::D2,
            Board::DigitalPin ce = Board::D3,
            Board::ExternalInterruptPin irq = Board::EXT0);
#elif defined(BOARD_ATMEGA2560)
  NRF24L01P(uint16_t net, uint8_t dev,
            Board::DigitalPin csn = Board::D53,
            Board::DigitalPin ce = Board::D48,
            Board::ExternalInterruptPin irq = Board::EXT4);
#else
  NRF24L01P(uint16_t net, uint8_t dev,
            Board::DigitalPin csn = Board::D10,
            Board::DigitalPin ce = Board::D9,
            Board::ExternalInterruptPin irq = Board::EXT0);
#endif

  void powerup();

  void standby();

  virtual void powerdown();

  virtual bool begin(const void* config = NULL);

  virtual bool end()
  {
    standby();
    return (true);
  }

  virtual bool available();

  virtual int send(uint8_t dest, uint8_t port, const iovec_t* vec);

  virtual int send(uint8_t dest, uint8_t port, const void* buf, size_t len);

  virtual int recv(uint8_t& src, uint8_t& port, void* buf, size_t count,
                   uint32_t ms = 0L);

  virtual void output_power_level(int8_t dBm);

  uint16_t trans() const
  {
    return (m_trans);
  }

  uint16_t retrans() const
  {
    return (m_retrans);
  }

  uint16_t drops() const
  {
    return (m_drops);
  }

protected:
  enum State {
    POWER_DOWN_STATE = 0,
    STANDBY_STATE,
    RX_STATE,
    TX_STATE
  } __attribute__((packed));

  enum Command {
    R_REGISTER = 0x00,          
    W_REGISTER = 0x20,          
    REG_MASK = 0x1f,            
    R_RX_PAYLOAD = 0x61,        
    W_TX_PAYLOAD = 0xa0,        
    FLUSH_TX = 0xe1,            
    FLUSH_RX = 0xe2,            
    REUSE_TX_PL = 0xe3,         
    R_RX_PL_WID = 0x60,         
    W_ACK_PAYLOAD = 0xa8,       
    PIPE_MASK = 0x07,           
    W_TX_PAYLOAD_NO_ACK = 0xb0, 
    NOP = 0xff                  
  } __attribute__((packed));

  uint8_t read(Command cmd);

  void read(Command cmd, void* buf, size_t size);

  void write(Command cmd);

  void write(Command cmd, uint8_t data);

  void write(Command cmd, const void* buf, size_t size);

  enum Register {
    CONFIG = 0x00,              
    EN_AA = 0x01,               
    EN_RXADDR = 0x02,           
    SETUP_AW = 0x03,            
    SETUP_RETR = 0x04,          
    RF_CH = 0x05,               
    RF_SETUP = 0x06,            
    STATUS = 0x07,              
    OBSERVE_TX = 0x08,          
    RPD = 0x09,                 
    RX_ADDR_P0 = 0x0a,          
    RX_ADDR_P1 = 0x0b,          
    RX_ADDR_P2 = 0x0c,          
    RX_ADDR_P3 = 0x0d,          
    RX_ADDR_P4 = 0x0e,          
    RX_ADDR_P5 = 0x0f,          
    TX_ADDR = 0x10,             
    RX_PW_P0 = 0x11,            
    RX_PW_P1 = 0x12,            
    RX_PW_P2 = 0x13,            
    RX_PW_P3 = 0x14,            
    RX_PW_P4 = 0x15,            
    RX_PW_P5 = 0x16,            
    FIFO_STATUS = 0x17,         
    DYNPD = 0x1c,               
    FEATURE = 0x1d              
  } __attribute__((packed));

  enum {
    MASK_RX_DR = 6,             
    MASK_TX_DS = 5,             
    MASK_MAX_RT = 4,            
    EN_CRC = 3,                 
    CRCO = 2,                   
    PWR_UP = 1,                 
    PRIM_RX = 0,                
  } __attribute__((packed));

  enum {
    POWER_DOWN = 0,             
    POWER_UP = _BV(PWR_UP)
  } __attribute__((packed));

  enum {
    ENAA_P5 = 5,                
    ENAA_P4 = 4,                
    ENAA_P3 = 3,                
    ENAA_P2 = 2,                
    ENAA_P1 = 1,                
    ENAA_P0 = 0,                
    ENAA_PA = 0x3f              
  } __attribute__((packed));

  enum {
    ERX_P5 = 5,                 
    ERX_P4 = 4,                 
    ERX_P3 = 3,                 
    ERX_P2 = 2,                 
    ERX_P1 = 1,                 
    ERX_P0 = 0,                 
    ERX_PA = 0x3f               
  } __attribute__((packed));

  enum {
    AW = 0,                     
    AW_3BYTES = 1,              
    AW_4BYTES = 2,              
    AW_5BYTES = 3               
  } __attribute__((packed));

  enum {
    ARD = 4,                    
    DEFAULT_ARD = 2,            
    ARC = 0,                    
    DEFAULT_ARC = 15            
  } __attribute__((packed));

  enum {
    CONT_WAVE = 7,              
    RF_DR_LOW = 5,              
    PLL_LOCK_SIGNAL = 4,        
    RF_DR_HIGH = 3,             
    RF_PWR = 1                  
  } __attribute__((packed));

  enum {
    RF_DR_1MBPS = 0,                    
    RF_DR_2MBPS = _BV(RF_DR_HIGH),      
    RF_DR_250KBPS = _BV(RF_DR_LOW)      
  } __attribute__((packed));

  enum {
    RF_PWR_18DBM = 0,           
    RF_PWR_12DBM = 2,           
    RF_PWR_6DBM = 4,            
    RF_PWR_0DBM = 6             
  } __attribute__((packed));

  enum {
    RX_DR = 6,                  
    TX_DS = 5,                  
    MAX_RT = 4,                 
    RX_P_NO = 1,                
    RX_P_NO_MASK = 0x0e,        
    RX_P_NO_NONE = 0x07,        
    TX_FIFO_FULL = 0            
  } __attribute__((packed));

  union status_t {
    uint8_t as_byte;            
    struct {
      uint8_t tx_full:1;        
      uint8_t rx_p_no:3;        
      uint8_t max_rt:1;         
      uint8_t tx_ds:1;          
      uint8_t rx_dr:1;          
      uint8_t reserved:1;
    };

    status_t(uint8_t value)
    {
      as_byte = value;
    }
  };

  enum  {
    PLOS_CNT = 4,               
    ARC_CNT = 0                 
  } __attribute__((packed));

  union observe_tx_t {
    uint8_t as_byte;            
    struct {
      uint8_t arc_cnt:4;        
      uint8_t plos_cnt:4;       
    };

    observe_tx_t(uint8_t value)
    {
      as_byte = value;
    }
  };

  enum {
    TX_REUSE = 6,               
    TX_FULL = 5,                
    TX_EMPTY = 4,               
    RX_FULL = 1,                
    RX_EMPTY = 0,               
  } __attribute__((packed));

  union fifo_status_t {
    uint8_t as_byte;            
    struct {
      uint8_t rx_empty:1;       
      uint8_t rx_full:1;        
      uint8_t reserved1:2;
      uint8_t tx_empty:1;       
      uint8_t tx_full:1;        
      uint8_t tx_reuse:1;       
      uint8_t reserved2:1;
    };

    fifo_status_t(uint8_t value)
    {
      as_byte = value;
    }
  };

  enum {
    DPL_P5 = 5,                 
    DPL_P4 = 4,                 
    DPL_P3 = 3,                 
    DPL_P2 = 2,                 
    DPL_P1 = 1,                 
    DPL_P0 = 0,                 
    DPL_PA = 0x3f               
  } __attribute__((packed));

  enum {
    EN_DPL = 2,                 
    EN_ACK_PAY = 1,             
    EN_DYN_ACK = 0              
  } __attribute__((packed));


  uint8_t read(Register reg)
  {
    return (read((Command) (R_REGISTER | (REG_MASK & reg))));
  }

  void read(Register reg, void* buf, size_t size)
  {
    read((Command) (R_REGISTER | (REG_MASK & reg)), buf, size);
  }

  void write(Register reg, uint8_t data)
  {
    write((Command) (W_REGISTER | (REG_MASK & reg)), data);
  }

  void write(Register reg, const void* buf, size_t size)
  {
    write((Command) (W_REGISTER | (REG_MASK & reg)), buf, size);
  }

  static const uint16_t Tpd2stby_ms = 3;
  static const uint16_t Tstby2a_us = 130;
  static const uint16_t Thce_us = 10;

  enum {
    AW_MAX = 5,                 
    PIPE_MAX = 6,               
  } __attribute__((packed));

  class IRQPin : public ExternalInterrupt {
  public:
    IRQPin(Board::ExternalInterruptPin pin,
           InterruptMode mode,
           NRF24L01P* nrf) :
      ExternalInterrupt(pin, mode),
      m_nrf(nrf)
    {}
    friend class NRF24L01P;
  private:
    NRF24L01P* m_nrf;           
  };

  OutputPin m_ce;               
  IRQPin m_irq;                 
  status_t m_status;            
  State m_state;                

  uint16_t m_trans;             
  uint16_t m_retrans;           
  uint16_t m_drops;             

  status_t read_status();

  fifo_status_t read_fifo_status()
  {
    return (read(FIFO_STATUS));
  }

  observe_tx_t read_observe_tx()
  {
    return (read(OBSERVE_TX));;
  }

  void transmit_mode(uint8_t dest);

  void receiver_mode();

  // Allow operators to access internals
  friend IOStream& operator<<(IOStream& outs, status_t status);
  friend IOStream& operator<<(IOStream& outs, fifo_status_t status);
  friend IOStream& operator<<(IOStream& outs, observe_tx_t observe);
};

IOStream& operator<<(IOStream& outs, NRF24L01P::status_t status);

IOStream& operator<<(IOStream& outs, NRF24L01P::fifo_status_t status);

IOStream& operator<<(IOStream& outs, NRF24L01P::observe_tx_t observe);

#endif
#endif