COSA
An Object-Oriented Platform for Arduino Programming
W5200.hh
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1 
21 #ifndef COSA_W5200_HH
22 #define COSA_W5200_HH
23 
24 #include "Cosa/Types.h"
25 
26 #if !defined(BOARD_ATTINY)
27 #include "Cosa/SPI.hh"
28 #include "Cosa/Socket.hh"
29 
57 class W5200 : private SPI::Driver {
58 public:
65  W5200(const uint8_t* mac = NULL, Board::DigitalPin csn = Board::D10);
66 
72  void addr(uint8_t ip[4], uint8_t subnet[4]);
73 
79  void dns_addr(uint8_t ip[4]) { memcpy(ip, m_dns, sizeof(m_dns)); }
80 
89  bool begin_P(const char* hostname, uint16_t timeout = 500);
90  bool begin_P(str_P hostname, uint16_t timeout = 500)
91  {
92  return (begin_P((const char*) hostname, timeout));
93  }
94 
103  bool begin(uint8_t ip[4] = NULL, uint8_t subnet[4] = NULL,
104  uint16_t timeout = 500);
105 
114  int bind(uint8_t ip[4], uint8_t subnet[4], uint8_t gateway[4] = NULL);
115 
124  Socket* socket(Socket::Protocol proto, uint16_t port = 0, uint8_t flag = 0);
125 
130  bool end();
131 
132 protected:
136  struct CommonRegister {
137  uint8_t MR;
138  uint8_t GAR[4];
139  uint8_t SUBR[4];
140  uint8_t SHAR[6];
141  uint8_t SIPR[4];
142  uint8_t reserved1[2];
143  uint8_t IR;
144  uint8_t IMR;
145  uint16_t RTR;
146  uint8_t RCR;
147  uint8_t reserved2[2];
148  uint8_t PATR[2];
149  uint8_t PPPALGO;
150  uint8_t VERSIONR;
151  uint8_t reserved3[8];
152  uint8_t PTIMER;
153  uint8_t PMAGIC;
154  uint8_t reserved4[6];
155  uint8_t INTLEVEL[2];
156  uint8_t reserved5[2];
157  uint8_t IR2;
158  uint8_t PSTATUS;
159  uint8_t IMR2;
160  };
161 
165  enum {
166  MR_RST = 0x80,
167  MR_WOL = 0x20,
168  MR_PB = 0x10,
169  MR_PPPoE = 0x08,
170  } __attribute__((packed));
171 
175  enum {
176  IR_CONFLICT = 0x80,
177  IR_PPPoE = 0x20,
178  } __attribute__((packed));
179 
183  enum {
184  IMR_CONFLICT = 0x80,
185  IMR_PPPoE = 0x20,
186  } __attribute__((packed));
187 
191  enum {
192  IR2_S7_INT = 0x80,
193  IR2_S6_INT = 0x40,
194  IR2_S5_INT = 0x20,
195  IR2_S4_INT = 0x10,
196  IR2_S3_INT = 0x08,
197  IR2_S2_INT = 0x04,
198  IR2_S1_INT = 0x02,
199  IR2_S0_INT = 0x01
200  } __attribute__((packed));
201 
205  enum {
206  IMR2_S7_INT = 0x80,
207  IMR2_S6_INT = 0x40,
208  IMR2_S5_INT = 0x20,
209  IMR2_S4_INT = 0x10,
210  IMR2_S3_INT = 0x08,
211  IMR2_S2_INT = 0x04,
212  IMR2_S1_INT = 0x02,
213  IMR2_S0_INT = 0x01
214  } __attribute__((packed));
215 
219  enum {
220  MEM_SIZE_00K = 0x00,
221  MEM_SIZE_01K = 0x01,
222  MEM_SIZE_02K = 0x02,
223  MEM_SIZE_04K = 0x04,
224  MEM_SIZE_08K = 0x08,
225  MEM_SIZE_16K = 0x10,
226  } __attribute__((packed));
227 
229  static const uint16_t COMMON_REGISTER_BASE = 0x0000;
230  static const uint16_t COMMON_REGISTER_SIZE = sizeof(CommonRegister);
231 
235  struct SocketRegister {
236  uint8_t MR;
237  uint8_t CR;
238  uint8_t IR;
239  uint8_t SR;
240  uint16_t PORT;
241  uint8_t DHAR[6];
242  uint8_t DIPR[4];
243  uint16_t DPORT;
244  uint16_t MSSR;
245  uint8_t PROTO;
246  uint8_t TOS;
247  uint8_t TTL;
248  uint8_t reserved1[7];
249  uint8_t RXMEM_SIZE;
250  uint8_t TXMEM_SIZE;
251  uint16_t TX_FSR;
252  uint16_t TX_RD;
253  uint16_t TX_WR;
254  uint16_t RX_RSR;
255  uint16_t RX_RD;
256  uint16_t RX_WR;
257  uint8_t IMR;
258  uint16_t FRAG;
259  uint8_t reserved2[208];
260  };
261 
265  enum {
266  MR_FLAG_MASK = 0xe0,
267  MR_MULTI = 0x80,
268  MR_MF = 0x40,
269  MR_ND = 0x20,
270  MR_MC = 0x20,
271  MR_PROTO_MASK = 0x0f,
273  MR_PROTO_TCP = 0x01,
274  MR_PROTO_UDP = 0x02,
275  MR_PROTO_IPRAW = 0x03,
278  } __attribute__((packed));
279 
283  enum {
284  CR_OPEN = 0x01,
285  CR_LISTEN = 0x02,
286  CR_CONNECT = 0x04,
287  CR_DISCON = 0x08,
288  CR_CLOSE = 0x10,
289  CR_SEND = 0x20,
290  CR_SEND_MAC = 0x21,
291  CR_SEND_KEEP = 0x22,
292  CR_RECV = 0x40,
293 #if 0
294  CR_PCON = 0x23,
295  CR_PDISCON = 0x24,
296  CR_PCR = 0x25,
297  CR_PCN = 0x26,
298  CR_PCJ = 0x27
299 #endif
300  } __attribute__((packed));
301 
305  enum {
306 #if 0
307  IR_PRECV = 0x80,
308  IR_PFAIL = 0x40,
309  IR_PNEXT = 0x20,
310 #endif
311  IR_SEND_OK = 0x10,
312  IR_TIMEOUT = 0x08,
313  IR_RECV = 0x04,
314  IR_DISCON = 0x02,
315  IR_CON = 0x01
316  } __attribute__((packed));
317 
321  enum {
322  SR_CLOSED = 0x00,
323  SR_ARP = 0x01,
324  SR_INIT = 0x13,
325  SR_LISTEN = 0x14,
326  SR_SYNSENT = 0x15,
327  SR_SYNRECV = 0x16,
329  SR_FIN_WAIT = 0x18,
330  SR_CLOSING = 0x1A,
331  SR_TIME_WAIT = 0x1B,
333  SR_LAST_ACK = 0x1D,
334  SR_UDP = 0x22,
335  SR_IPRAW = 0x32,
336  SR_MACRAW = 0x42,
337  SR_PPPoE = 0x5F
338  } __attribute__((packed));
339 
341  static const uint16_t SOCKET_REGISTER_BASE = 0x4000;
342  static const uint16_t SOCKET_REGISTER_SIZE = sizeof(SocketRegister);
343 
345  static const uint16_t TX_MEMORY_BASE = 0x8000;
346  static const uint16_t TX_MEMORY_MAX = 0x4000;
347 
349  static const uint16_t RX_MEMORY_BASE = 0xC000;
350  static const uint16_t RX_MEMORY_MAX = 0x4000;
351 
353  static const size_t BUF_MAX = 2048;
354  static const uint16_t BUF_MASK = 0x07ff;
355 
357  static const size_t MSG_MAX = BUF_MAX / 2;
358 
360  static const uint8_t SOCK_MAX = 8;
361 
363  static const uint8_t DNS_RETRY_MAX = 4;
364 
365 public:
370  class Driver : public Socket {
371  friend class W5200;
372  public:
374  Driver() : Socket() {}
375 
381  virtual int available();
382 
388  virtual int room();
389 
392 
395 
403  virtual int read(void* buf, size_t size);
404 
410  virtual int flush();
411 
422  virtual int open(Protocol proto, uint16_t port, uint8_t flag);
423 
433  virtual int close();
434 
442  virtual int listen();
443 
453  virtual int accept();
454 
464  virtual int connect(uint8_t addr[4], uint16_t port);
465 
474  virtual int connect(const char* hostname, uint16_t port);
475 
483  virtual int is_connected();
484 
491  virtual int disconnect();
492 
502  virtual int datagram(uint8_t addr[4], uint16_t port);
503 
515  virtual int recv(void* buf, size_t len);
516 
530  virtual int recv(void* buf, size_t len,
531  uint8_t src[4], uint16_t& port);
532 
533  protected:
536 
539 
541  uint16_t m_tx_buf;
542 
544  uint16_t m_tx_offset;
545 
547  uint16_t m_tx_len;
548 
550  uint16_t m_rx_buf;
551 
560  int dev_read(void* buf, size_t len);
561 
571  int dev_write(const void* buf, size_t len, bool progmem);
572 
576  void dev_flush();
577 
583  void dev_setup();
584 
595  virtual int write(const void* buf, size_t size, bool progmem);
596 
609  virtual int send(const void* buf, size_t len, bool progmem);
610 
625  virtual int send(const void* buf, size_t len,
626  uint8_t dest[4], uint16_t port,
627  bool progmem);
628  };
629 
631  static const uint8_t MAC[6] PROGMEM;
632 
633 protected:
636 
639 
641  uint16_t m_local;
642 
644  const uint8_t* m_mac;
645 
647  uint8_t m_dns[4];
648 
650  enum {
651  OP_WRITE = 0x80,
652  OP_READ = 0x00
653  } __attribute__((packed));
654 
660  void write(uint16_t addr, uint8_t data)
661  {
662  write(addr, &data, 1);
663  }
664 
672  void write(uint16_t addr, const void* buf, size_t len, bool progmem = false);
673 
681  void write_P(uint16_t addr, const void* buf, size_t len)
682  {
683  write(addr, buf, len, true);
684  }
685 
690  uint8_t read(uint16_t addr);
691 
699  void read(uint16_t addr, void* buf, size_t len);
700 
707  void issue(uint16_t addr, uint8_t cmd);
708 };
709 
710 #endif
711 #endif
Mask PPPoE Connection Close.
Definition: W5200.hh:185
uint16_t TX_FSR
TX Free Size Register.
Definition: W5200.hh:251
Definition: Socket.hh:31
static const uint16_t RX_MEMORY_BASE
Definition: W5200.hh:349
static const uint16_t SOCKET_REGISTER_SIZE
Definition: W5200.hh:342
static const uint16_t RX_MEMORY_MAX
Definition: W5200.hh:350
void dns_addr(uint8_t ip[4])
Definition: W5200.hh:79
uint8_t m_dns[4]
Definition: W5200.hh:647
Mask IP Conflict.
Definition: W5200.hh:184
Mask occurrence of Socket 3 Interrupt.
Definition: W5200.hh:210
uint8_t PATR[2]
Authentication Type in PPPoE.
Definition: W5200.hh:148
uint8_t PTIMER
PPP LCP Request Timer Register.
Definition: W5200.hh:152
Occurrence of Socket 7 Interrupt.
Definition: W5200.hh:192
virtual int write(const void *buf, size_t size)
Close socket.
Definition: W5200.hh:288
Multicasting.
Definition: W5200.hh:267
Initiate socket according to MR.
Definition: W5200.hh:284
virtual int read(void *buf, size_t size)
uint8_t MR
Mode Register.
Definition: W5200.hh:236
Occurrence of Socket 0 Interrupt.
Definition: W5200.hh:199
Connection termination.
Definition: W5200.hh:314
bool end()
uint16_t PORT
Source Port Register.
Definition: W5200.hh:240
Definition: W5200.hh:57
#define NULL
Definition: Types.h:101
Flag mask.
Definition: W5200.hh:266
static const uint16_t TX_MEMORY_BASE
Definition: W5200.hh:345
uint8_t reserved3[8]
Reserved.
Definition: W5200.hh:151
uint16_t m_rx_buf
Definition: W5200.hh:550
TCP: Initiate client mode.
Definition: W5200.hh:286
CommonRegister * m_creg
Definition: W5200.hh:638
static const uint16_t COMMON_REGISTER_SIZE
Definition: W5200.hh:230
Timeout occured.
Definition: W5200.hh:312
uint8_t SUBR[4]
Subnet mask Address Register.
Definition: W5200.hh:139
void issue(uint16_t addr, uint8_t cmd)
void addr(uint8_t ip[4], uint8_t subnet[4])
Protocol
Definition: Socket.hh:37
uint8_t IR
Interrupt Register.
Definition: W5200.hh:238
uint16_t RX_WR
RX Write Pointer Register.
Definition: W5200.hh:256
Occurrence of Socket 5 Interrupt.
Definition: W5200.hh:194
bool begin_P(str_P hostname, uint16_t timeout=500)
Definition: W5200.hh:90
Connection established.
Definition: W5200.hh:315
uint16_t m_tx_offset
Definition: W5200.hh:544
uint16_t MSSR
Maximum Segment Size Register.
Definition: W5200.hh:244
SocketRegister * m_sreg
Definition: W5200.hh:535
static const uint16_t COMMON_REGISTER_BASE
Definition: W5200.hh:229
Occurrence of Socket 3 Interrupt.
Definition: W5200.hh:196
uint8_t reserved1[2]
Reserved.
Definition: W5200.hh:142
uint16_t RX_RSR
RX Received Size Register.
Definition: W5200.hh:254
TCP: Disconnect server/client.
Definition: W5200.hh:287
Mask occurrence of Socket 6 Interrupt.
Definition: W5200.hh:207
Occurrence of Socket 6 Interrupt.
Definition: W5200.hh:193
uint8_t RXMEM_SIZE
RX Memory Size Register.
Definition: W5200.hh:249
uint8_t GAR[4]
Gateway Address Register.
Definition: W5200.hh:138
uint8_t VERSIONR
Chip Version.
Definition: W5200.hh:150
static const size_t BUF_MAX
Definition: W5200.hh:353
uint16_t DPORT
Destination Port Register.
Definition: W5200.hh:243
bool begin_P(const char *hostname, uint16_t timeout=500)
uint8_t PMAGIC
PPP LCP Magic number.
Definition: W5200.hh:153
const uint8_t * m_mac
Definition: W5200.hh:644
uint16_t TX_WR
TX Write Pointer Register.
Definition: W5200.hh:253
static const uint8_t DNS_RETRY_MAX
Definition: W5200.hh:363
MAC Filter.
Definition: W5200.hh:268
uint8_t IMR
Interrupt Mask Register.
Definition: W5200.hh:257
uint16_t m_tx_len
Definition: W5200.hh:547
Mask occurrence of Socket 5 Interrupt.
Definition: W5200.hh:208
int bind(uint8_t ip[4], uint8_t subnet[4], uint8_t gateway[4]=NULL)
W5200 * m_dev
Definition: W5200.hh:538
Use No Delay ACK.
Definition: W5200.hh:269
S/W Reset.
Definition: W5200.hh:166
uint8_t IMR
Interrupt Mask Register.
Definition: W5200.hh:144
const class prog_str * str_P
Definition: Types.h:187
uint8_t CR
Command Register.
Definition: W5200.hh:237
uint8_t SHAR[6]
Source Hardware Address Register.
Definition: W5200.hh:140
Occurrence of Socket 4 Interrupt.
Definition: W5200.hh:195
uint8_t SR
Status Register.
Definition: W5200.hh:239
UDP: Transmit data.
Definition: W5200.hh:290
uint8_t TOS
IP TOS.
Definition: W5200.hh:246
Multicast version.
Definition: W5200.hh:270
Mask occurrence of Socket 7 Interrupt.
Definition: W5200.hh:206
uint8_t PROTO
Protocol in IP Raw mode.
Definition: W5200.hh:245
uint8_t RCR
Retry Count Register.
Definition: W5200.hh:146
Driver m_sock[SOCK_MAX]
Definition: W5200.hh:635
IOStream & flush(IOStream &outs)
Definition: IOStream.hh:853
uint8_t PSTATUS
Socket Interrupt Register.
Definition: W5200.hh:158
PPPoE Connection Close.
Definition: W5200.hh:177
uint8_t IMR2
Socket Interrupt Register Mask.
Definition: W5200.hh:159
uint8_t MR
Mode Register.
Definition: W5200.hh:137
uint16_t m_tx_buf
Definition: W5200.hh:541
Occurrence of Socket 2 Interrupt.
Definition: W5200.hh:197
uint8_t IR2
Socket Interrupt Register.
Definition: W5200.hh:157
Mask occurrence of Socket 4 Interrupt.
Definition: W5200.hh:209
void write_P(uint16_t addr, const void *buf, size_t len)
Definition: W5200.hh:681
uint8_t SIPR[4]
Source IP Address Register.
Definition: W5200.hh:141
Mask occurrence of Socket 0 Interrupt.
Definition: W5200.hh:213
static const uint8_t MAC[6]
Definition: W5200.hh:631
TCP: Check connection status.
Definition: W5200.hh:291
uint16_t TX_RD
TX Read Pointer Register.
Definition: W5200.hh:252
static const uint16_t TX_MEMORY_MAX
Definition: W5200.hh:346
Mask occurrence of Socket 2 Interrupt.
Definition: W5200.hh:211
static const uint8_t SOCK_MAX
Definition: W5200.hh:360
Wake on LAN.
Definition: W5200.hh:167
uint8_t TTL
IP TTL.
Definition: W5200.hh:247
static const uint16_t BUF_MASK
Definition: W5200.hh:354
Socket * socket(Socket::Protocol proto, uint16_t port=0, uint8_t flag=0)
Occurrence of Socket 1 Interrupt.
Definition: W5200.hh:198
Ping Block Mode.
Definition: W5200.hh:168
uint16_t FRAG
Fragment Register.
Definition: W5200.hh:258
Mask occurrence of Socket 1 Interrupt.
Definition: W5200.hh:212
uint8_t read(uint16_t addr)
uint8_t reserved4[6]
Reserved.
Definition: W5200.hh:154
uint16_t m_local
Definition: W5200.hh:641
uint16_t RTR
Retry Time Register.
Definition: W5200.hh:145
uint8_t INTLEVEL[2]
Interrupt Low Level Timer.
Definition: W5200.hh:155
uint8_t reserved2[2]
Reserved.
Definition: W5200.hh:147
PPPoE Mode.
Definition: W5200.hh:169
TCP: Initiate server mode.
Definition: W5200.hh:285
Transmit data according to TX_WR.
Definition: W5200.hh:289
uint16_t RX_RD
RX Read Pointer Register.
Definition: W5200.hh:255
static const size_t MSG_MAX
Definition: W5200.hh:357
Received data.
Definition: W5200.hh:313
uint8_t PPPALGO
Authentication Algorithm in PPPoE.
Definition: W5200.hh:149
static const uint16_t SOCKET_REGISTER_BASE
Definition: W5200.hh:341
Protocol.
Definition: W5200.hh:271
bool begin(uint8_t ip[4]=NULL, uint8_t subnet[4]=NULL, uint16_t timeout=500)
Definition: W5200.cpp:71
IP Conflict.
Definition: W5200.hh:176
uint8_t reserved5[2]
Reserved.
Definition: W5200.hh:156
Receiving packet to RX_RD.
Definition: W5200.hh:292
Send operation is completed.
Definition: W5200.hh:311
uint8_t IR
Interrupt Register.
Definition: W5200.hh:143
W5200(const uint8_t *mac=NULL, Board::DigitalPin csn=Board::D10)
void write(uint16_t addr, uint8_t data)
Definition: W5200.hh:660
uint8_t TXMEM_SIZE
TX Memory Size Register.
Definition: W5200.hh:250