L3G4200D.hh

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#ifndef COSA_L3G4200D_HH
#define COSA_L3G4200D_HH

#include "Cosa/TWI.hh"
#include "Cosa/IOStream.hh"

class L3G4200D : private TWI::Driver {
public:
  L3G4200D(uint8_t subaddr = 0) : TWI::Driver(0x68 | (subaddr != 0)) {}

  bool begin();

  bool end();

  struct sample_t {
    int x;
    int y;
    int z;
  };

  void sample(sample_t& s)
    __attribute__((always_inline))
  {
    read(OUT, &s, sizeof(s));
  }

protected:
  enum Register {
    WHO_A_I = 0x0F,             
    CTRL_REG1 = 0x20,           
    CTRL_REG2 = 0x21,           
    CTRL_REG3 = 0x22,           
    CTRL_REG4 = 0x23,           
    CTRL_REG5 = 0x24,           
    REFERENCE = 0x25,           
    OUT_TEMP = 0x26,            
    STATUS_REG = 0x27,          
    OUT = 0x28,                 
    OUT_X = 0x28,               
    OUT_X_L = 0x28,             
    OUT_X_H = 0x29,             
    OUT_Y = 0x2A,               
    OUT_Y_L = 0x2A,             
    OUT_Y_H = 0x2B,             
    OUT_Z = 0x2C,               
    OUT_Z_L = 0x2C,             
    OUT_Z_H = 0x2D,             
    FIFO_CTRL_REG = 0x2E,       
    FIFO_SRC_REG = 0x2F,        
    INT1_CFG = 0x30,            
    INT1_SRC = 0x31,            
    INT1_TSH = 0x32,            
    INT1_TSH_XH = 0x32,         
    INT1_TSH_XL = 0x33,         
    INT1_TSH_YH = 0x34,         
    INT1_TSH_YL = 0x35,         
    INT1_TSH_ZH = 0x36,         
    INT1_TSH_ZL = 0x37,         
    INT1_DURATION = 0x38        
  } __attribute__((packed));

  static const uint8_t AUTO_INC = 0x80;

  union ctrl_reg1_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t Xen:1;            
      uint8_t Yen:1;            
      uint8_t Zen:1;            
      uint8_t PD:1;             
      uint8_t BW:2;             
      uint8_t DR:2;             
    };
    ctrl_reg1_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };
  enum {                        
    DR_100_HZ,                  
    DR_200_HZ,                  
    DR_400_HZ,                  
    DR_800_HZ                   
  } __attribute__((packed));
  enum {                        
    BW_12_5,                    
    BW_25,
    BW_50,
    BW_110
  } __attribute__((packed));

  union ctrl_reg2_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t HPCF:4;           
      uint8_t HPM:2;            
      uint8_t reserved:2;       
    };
    ctrl_reg2_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };
  enum {                        
    HPM_NORMAL = 0,             
    HPM_MODE = 1,               
    HPM_AUTORESET = 3           
  } __attribute__((packed));

  union ctrl_reg3_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t I2_Empty:1;       
      uint8_t I2_ORun:1;        
      uint8_t I2_WTM:1;         
      uint8_t I2_DRDY:1;        
      uint8_t PP_OD:1;          
      uint8_t H_Lactive:1;      
      uint8_t I1_Boot:1;        
      uint8_t I1_Int1:1;        
    };
    ctrl_reg3_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  union ctrl_reg4_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t SIM:1;            
      uint8_t ST:2;             
      uint8_t reserved:1;
      uint8_t FS:2;             
      uint8_t BLE:1;            
      uint8_t BDU:1;            
    };
    ctrl_reg4_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  union ctrl_reg5_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t Out_Sel:2;        
      uint8_t INT1_Sel:2;       
      uint8_t HPen:1;           
      uint8_t FIFO_EN:1;        
      uint8_t BOOT:1;           
    };
    ctrl_reg5_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  union status_reg_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t XDA:1;            
      uint8_t YDA:1;            
      uint8_t ZDA:1;            
      uint8_t XYZDA:1;          
      uint8_t XOR:1;            
      uint8_t YOR:1;            
      uint8_t ZOR:1;            
      uint8_t XYZOR:1;          
    };
    status_reg_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  union fifo_ctrl_reg_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t WTM:5;            
      uint8_t FM:3;             
    };
    fifo_ctrl_reg_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };
  enum {                        
    FM_BYPASS,                  
    FM_FIFO,                    
    FM_STREAM,                  
    FM_STREAM_TO_FIFO,          
    FM_BYPASS_TO_STREAM         
  } __attribute__((packed));

  union fifo_src_reg_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t FSS:5;            
      uint8_t EMPTY:1;          
      uint8_t OVRN:1;           
      uint8_t WTM:1;            
    };
    fifo_src_reg_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  union int1_cfg_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t XLIE:1;           
      uint8_t XHIE:1;           
      uint8_t YLIE:1;           
      uint8_t YHIE:1;           
      uint8_t ZLIE:1;           
      uint8_t ZHIE:1;           
      uint8_t LIR:1;            
      uint8_t AND_OR:1;         
    };
    int1_cfg_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  struct int1_src_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t XL:1;             
      uint8_t XH:1;             
      uint8_t YL:1;             
      uint8_t YH:1;             
      uint8_t ZL:1;             
      uint8_t ZH:1;             
      uint8_t IA:1;             
      uint8_t reserved:1;
    };
    int1_src_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  struct int1_duration_t {
    uint8_t as_uint8;           
    struct {                    
      uint8_t value:7;          
      uint8_t WAIT:1;           
    };
    int1_duration_t(uint8_t value = 0)
    {
      as_uint8 = value;
    }
    operator uint8_t()
    {
      return (as_uint8);
    }
  };

  void write(Register reg, uint8_t value);

  void write(Register reg, void* buffer, uint8_t count);

  uint8_t read(Register reg);

  void read(Register reg, void* buffer, uint8_t count);
};

extern IOStream& operator<<(IOStream& outs, L3G4200D& gyroscope);

#endif