COSA
An Object-Oriented Platform for Arduino Programming
W5500::CommonRegister Struct Reference

#include <W5500.hh>

Collaboration diagram for W5500::CommonRegister:
Collaboration graph

Public Attributes

uint8_t MR
 Mode Register. More...
 
uint8_t GAR [4]
 Gateway Address Register. More...
 
uint8_t SUBR [4]
 Subnet mask Address Register. More...
 
uint8_t SHAR [6]
 Source Hardware Address Register. More...
 
uint8_t SIPR [4]
 Source IP Address Register. More...
 
uint16_t INTLEVEL
 Interrupt Low level Timer. More...
 
uint8_t IR
 Interrupt Register. More...
 
uint8_t IMR
 Interrupt Mask Register. More...
 
uint8_t SIR
 Socket Interrupt Register. More...
 
uint8_t SIMR
 Socket Interrupt Mask Register. More...
 
uint16_t RTR
 Retry Time Register. More...
 
uint8_t RCR
 Retry Count Register. More...
 
uint8_t PTIMER
 PPP LCP Request Timer Register. More...
 
uint8_t PMAGIC
 PPP LCP Magic number. More...
 
uint8_t PHAR [6]
 PPP Destination MAC Address. More...
 
uint16_t PSID
 PPP Session Identification. More...
 
uint16_t PMRU
 PPP Maximum Segment Size. More...
 
uint8_t UIPR [4]
 Unreachable IP Address Register. More...
 
uint16_t UPORTR
 Unreachable Port Register. More...
 
uint8_t PHYCFGR
 PHY COnfiguration. More...
 
uint8_t reserved [10]
 Reserved. More...
 
uint8_t VERSIONR
 Chip Version. More...
 

Detailed Description

Common Registers (chap. 3.1, pp. 30), big-endian 16-bit values.

Definition at line 136 of file W5500.hh.

Member Data Documentation

uint8_t W5500::CommonRegister::GAR[4]

Gateway Address Register.

Definition at line 138 of file W5500.hh.

uint8_t W5500::CommonRegister::IMR

Interrupt Mask Register.

Definition at line 144 of file W5500.hh.

uint16_t W5500::CommonRegister::INTLEVEL

Interrupt Low level Timer.

Definition at line 142 of file W5500.hh.

uint8_t W5500::CommonRegister::IR

Interrupt Register.

Definition at line 143 of file W5500.hh.

uint8_t W5500::CommonRegister::MR

Mode Register.

Definition at line 137 of file W5500.hh.

uint8_t W5500::CommonRegister::PHAR[6]

PPP Destination MAC Address.

Definition at line 151 of file W5500.hh.

uint8_t W5500::CommonRegister::PHYCFGR

PHY COnfiguration.

Definition at line 156 of file W5500.hh.

uint8_t W5500::CommonRegister::PMAGIC

PPP LCP Magic number.

Definition at line 150 of file W5500.hh.

uint16_t W5500::CommonRegister::PMRU

PPP Maximum Segment Size.

Definition at line 153 of file W5500.hh.

uint16_t W5500::CommonRegister::PSID

PPP Session Identification.

Definition at line 152 of file W5500.hh.

uint8_t W5500::CommonRegister::PTIMER

PPP LCP Request Timer Register.

Definition at line 149 of file W5500.hh.

uint8_t W5500::CommonRegister::RCR

Retry Count Register.

Definition at line 148 of file W5500.hh.

uint8_t W5500::CommonRegister::reserved[10]

Reserved.

Definition at line 157 of file W5500.hh.

uint16_t W5500::CommonRegister::RTR

Retry Time Register.

Definition at line 147 of file W5500.hh.

uint8_t W5500::CommonRegister::SHAR[6]

Source Hardware Address Register.

Definition at line 140 of file W5500.hh.

uint8_t W5500::CommonRegister::SIMR

Socket Interrupt Mask Register.

Definition at line 146 of file W5500.hh.

uint8_t W5500::CommonRegister::SIPR[4]

Source IP Address Register.

Definition at line 141 of file W5500.hh.

uint8_t W5500::CommonRegister::SIR

Socket Interrupt Register.

Definition at line 145 of file W5500.hh.

uint8_t W5500::CommonRegister::SUBR[4]

Subnet mask Address Register.

Definition at line 139 of file W5500.hh.

uint8_t W5500::CommonRegister::UIPR[4]

Unreachable IP Address Register.

Definition at line 154 of file W5500.hh.

uint16_t W5500::CommonRegister::UPORTR

Unreachable Port Register.

Definition at line 155 of file W5500.hh.

uint8_t W5500::CommonRegister::VERSIONR

Chip Version.

Definition at line 158 of file W5500.hh.


The documentation for this struct was generated from the following file: