COSA
An Object-Oriented Platform for Arduino Programming
W5100.hh
Go to the documentation of this file.
1 
21 #ifndef COSA_W5100_HH
22 #define COSA_W5100_HH
23 
24 #include "Cosa/Types.h"
25 
26 #if !defined(BOARD_ATTINY)
27 #include "Cosa/SPI.hh"
28 #include "Cosa/Socket.hh"
29 
57 class W5100 : private SPI::Driver {
58 public:
65  W5100(const uint8_t* mac = NULL, Board::DigitalPin csn = Board::D10);
66 
72  void addr(uint8_t ip[4], uint8_t subnet[4]);
73 
79  void dns_addr(uint8_t ip[4]) { memcpy(ip, m_dns, sizeof(m_dns)); }
80 
89  bool begin_P(const char* hostname, uint16_t timeout = 500);
90  bool begin_P(str_P hostname, uint16_t timeout = 500)
91  {
92  return (begin_P((const char*) hostname, timeout));
93  }
94 
103  bool begin(uint8_t ip[4] = NULL, uint8_t subnet[4] = NULL,
104  uint16_t timeout = 500);
105 
114  int bind(uint8_t ip[4], uint8_t subnet[4], uint8_t gateway[4] = NULL);
115 
124  Socket* socket(Socket::Protocol proto, uint16_t port = 0, uint8_t flag = 0);
125 
130  bool end();
131 
132 protected:
136  struct CommonRegister {
137  uint8_t MR;
138  uint8_t GAR[4];
139  uint8_t SUBR[4];
140  uint8_t SHAR[6];
141  uint8_t SIPR[4];
142  uint8_t reserved1[2];
143  uint8_t IR;
144  uint8_t IMR;
145  uint16_t RTR;
146  uint8_t RCR;
147  uint8_t RMSR;
148  uint8_t TMSR;
149  uint8_t PATR[2];
150  uint8_t reserved2[10];
151  uint8_t PTIMER;
152  uint8_t PMAGIC;
153  uint8_t UIPR[4];
154  uint16_t UPORT;
155  };
156 
160  enum {
161  MR_RST = 0x80,
162  MR_PB = 0x10,
163  MR_PPPoE = 0x08,
164  MR_AI = 0x02,
165  MR_IND = 0x01
166  } __attribute__((packed));
167 
171  enum {
172  IR_CONFLICT = 0x80,
173  IR_UNREACH = 0x40,
174  IR_PPPoE = 0x20,
175  IR_S3_INT = 0x08,
176  IR_S2_INT = 0x04,
177  IR_S1_INT = 0x02,
178  IR_S0_INT = 0x01
179  } __attribute__((packed));
180 
184  enum {
185  IMR_CONFLICT = 0x80,
186  IMR_UNREACH = 0x40,
187  IMR_PPPoE = 0x20,
188  IMR_S3_INT = 0x08,
189  IMR_S2_INT = 0x04,
190  IMR_S1_INT = 0x02,
191  IMR_S0_INT = 0x01
192  } __attribute__((packed));
193 
197  enum {
202  } __attribute__((packed));
203 
205  static const uint16_t COMMON_REGISTER_BASE = 0x0000;
206  static const uint16_t COMMON_REGISTER_SIZE = sizeof(CommonRegister);
207 
211  struct SocketRegister {
212  uint8_t MR;
213  uint8_t CR;
214  uint8_t IR;
215  uint8_t SR;
216  uint16_t PORT;
217  uint8_t DHAR[6];
218  uint8_t DIPR[4];
219  uint16_t DPORT;
220  uint16_t MSSR;
221  uint8_t PROTO;
222  uint8_t TOS;
223  uint8_t TTL;
224  uint8_t reserved1[9];
225  uint16_t TX_FSR;
226  uint16_t TX_RD;
227  uint16_t TX_WR;
228  uint16_t RX_RSR;
229  uint16_t RX_RD;
230  uint8_t reserved2[2];
231  uint8_t reserved3[212];
232  };
233 
237  enum {
238  MR_FLAG_MASK = 0xe0,
239  MR_MULTI = 0x80,
240  MR_MF = 0x40,
241  MR_ND = 0x20,
242  MR_MC = 0x20,
243  MR_PROTO_MASK = 0x0f,
245  MR_PROTO_TCP = 0x01,
246  MR_PROTO_UDP = 0x02,
247  MR_PROTO_IPRAW = 0x03,
250  } __attribute__((packed));
251 
255  enum {
256  CR_OPEN = 0x01,
257  CR_LISTEN = 0x02,
258  CR_CONNECT = 0x04,
259  CR_DISCON = 0x08,
260  CR_CLOSE = 0x10,
261  CR_SEND = 0x20,
262  CR_SEND_MAC = 0x21,
263  CR_SEND_KEEP = 0x22,
264  CR_RECV = 0x40
265  } __attribute__((packed));
266 
270  enum {
271  IR_SEND_OK = 0x10,
272  IR_TIMEOUT = 0x08,
273  IR_RECV = 0x04,
274  IR_DISCON = 0x02,
275  IR_CON = 0x01
276  } __attribute__((packed));
277 
281  enum {
282  SR_CLOSED = 0x00,
283  SR_ARP = 0x01,
284  SR_INIT = 0x13,
285  SR_LISTEN = 0x14,
286  SR_SYNSENT = 0x15,
287  SR_SYNRECV = 0x16,
289  SR_FIN_WAIT = 0x18,
290  SR_CLOSING = 0x1A,
291  SR_TIME_WAIT = 0x1B,
293  SR_LAST_ACK = 0x1D,
294  SR_UDP = 0x22,
295  SR_IPRAW = 0x32,
296  SR_MACRAW = 0x42,
297  SR_PPPoE = 0x5F
298  } __attribute__((packed));
299 
301  static const uint16_t SOCKET_REGISTER_BASE = 0x0400;
302  static const uint16_t SOCKET_REGISTER_SIZE = sizeof(SocketRegister);
303 
305  static const uint16_t TX_MEMORY_BASE = 0x4000;
306  static const uint16_t TX_MEMORY_MAX = 0x2000;
307 
309  static const uint16_t RX_MEMORY_BASE = 0x6000;
310  static const uint16_t RX_MEMORY_MAX = 0x2000;
311 
313  static const size_t BUF_MAX = 2048;
314  static const uint16_t BUF_MASK = 0x07ff;
315  static const uint8_t TX_MEMORY_SIZE = 0x55;
316  static const uint8_t RX_MEMORY_SIZE = 0x55;
317 
319  static const size_t MSG_MAX = BUF_MAX / 2;
320 
322  static const uint8_t SOCK_MAX = 4;
323 
325  static const uint8_t DNS_RETRY_MAX = 4;
326 
327 public:
332  class Driver : public Socket {
333  friend class W5100;
334  public:
336  Driver() : Socket() {}
337 
343  virtual int available();
344 
350  virtual int room();
351 
354 
357 
365  virtual int read(void* buf, size_t size);
366 
372  virtual int flush();
373 
384  virtual int open(Protocol proto, uint16_t port, uint8_t flag);
385 
395  virtual int close();
396 
404  virtual int listen();
405 
415  virtual int accept();
416 
426  virtual int connect(uint8_t addr[4], uint16_t port);
427 
436  virtual int connect(const char* hostname, uint16_t port);
437 
445  virtual int is_connected();
446 
453  virtual int disconnect();
454 
464  virtual int datagram(uint8_t addr[4], uint16_t port);
465 
477  virtual int recv(void* buf, size_t len);
478 
492  virtual int recv(void* buf, size_t len,
493  uint8_t src[4], uint16_t& port);
494 
495  protected:
498 
501 
503  uint16_t m_tx_buf;
504 
506  uint16_t m_tx_offset;
507 
509  uint16_t m_tx_len;
510 
512  uint16_t m_rx_buf;
513 
522  int dev_read(void* buf, size_t len);
523 
533  int dev_write(const void* buf, size_t len, bool progmem);
534 
538  void dev_flush();
539 
545  void dev_setup();
546 
557  virtual int write(const void* buf, size_t size, bool progmem);
558 
571  virtual int send(const void* buf, size_t len, bool progmem);
572 
587  virtual int send(const void* buf, size_t len,
588  uint8_t dest[4], uint16_t port,
589  bool progmem);
590  };
591 
593  static const uint8_t MAC[6] PROGMEM;
594 
595 protected:
598 
601 
603  uint16_t m_local;
604 
606  const uint8_t* m_mac;
607 
609  uint8_t m_dns[4];
610 
612  enum {
613  OP_WRITE = 0xf0,
614  OP_READ = 0x0f
615  } __attribute__((packed));
616 
622  void write(uint16_t addr, uint8_t data)
623  {
624  write(addr, &data, 1);
625  }
626 
634  void write(uint16_t addr, const void* buf, size_t len, bool progmem=false);
635 
643  void write_P(uint16_t addr, const void* buf, size_t len)
644  {
645  write(addr, buf, len, true);
646  }
647 
652  uint8_t read(uint16_t addr);
653 
661  void read(uint16_t addr, void* buf, size_t len);
662 
669  void issue(uint16_t addr, uint8_t cmd);
670 };
671 
672 #endif
673 #endif
uint8_t IMR
Interrupt Mask Register.
Definition: W5100.hh:144
Transmit data according to TX_WR.
Definition: W5100.hh:261
Definition: Socket.hh:31
uint8_t SR
Status Register.
Definition: W5100.hh:215
uint16_t DPORT
Destination Port Register.
Definition: W5100.hh:219
uint8_t UIPR[4]
Unreachable IP Address Register.
Definition: W5100.hh:153
static const uint16_t COMMON_REGISTER_BASE
Definition: W5100.hh:205
Multicast version.
Definition: W5100.hh:242
uint16_t RTR
Retry Time Register.
Definition: W5100.hh:145
uint8_t reserved1[2]
Reserved.
Definition: W5100.hh:142
Mask occurrence of Socket 3 Interrupt.
Definition: W5100.hh:188
void addr(uint8_t ip[4], uint8_t subnet[4])
static const uint16_t SOCKET_REGISTER_BASE
Definition: W5100.hh:301
uint8_t RCR
Retry Count Register.
Definition: W5100.hh:146
SocketRegister * m_sreg
Definition: W5100.hh:497
Protocol.
Definition: W5100.hh:243
uint16_t m_tx_offset
Definition: W5100.hh:506
MAC Filter.
Definition: W5100.hh:240
Multicasting.
Definition: W5100.hh:239
void dns_addr(uint8_t ip[4])
Definition: W5100.hh:79
static const size_t BUF_MAX
Definition: W5100.hh:313
virtual int write(const void *buf, size_t size)
virtual int read(void *buf, size_t size)
uint8_t SIPR[4]
Source IP Address Register.
Definition: W5100.hh:141
Definition: W5100.hh:57
#define NULL
Definition: Types.h:101
uint8_t read(uint16_t addr)
uint8_t MR
Mode Register.
Definition: W5100.hh:137
bool begin_P(str_P hostname, uint16_t timeout=500)
Definition: W5100.hh:90
uint16_t m_rx_buf
Definition: W5100.hh:512
uint8_t PTIMER
PPP LCP Request Timer Register.
Definition: W5100.hh:151
Occurrence of Socket 0 Interrupt.
Definition: W5100.hh:178
uint8_t TTL
IP TTL.
Definition: W5100.hh:223
Protocol
Definition: Socket.hh:37
uint8_t RMSR
RX Memory Size Register.
Definition: W5100.hh:147
uint8_t GAR[4]
Gateway Address Register.
Definition: W5100.hh:138
Send operation is completed.
Definition: W5100.hh:271
uint8_t m_dns[4]
Definition: W5100.hh:609
uint8_t reserved2[10]
Reserved.
Definition: W5100.hh:150
static const uint8_t RX_MEMORY_SIZE
Definition: W5100.hh:316
static const size_t MSG_MAX
Definition: W5100.hh:319
static const uint16_t SOCKET_REGISTER_SIZE
Definition: W5100.hh:302
static const uint16_t COMMON_REGISTER_SIZE
Definition: W5100.hh:206
TCP: Initiate client mode.
Definition: W5100.hh:258
uint16_t UPORT
Unreachable Port Register.
Definition: W5100.hh:154
uint8_t SUBR[4]
Subnet mask Address Register.
Definition: W5100.hh:139
uint16_t PORT
Source Port Register.
Definition: W5100.hh:216
uint16_t MSSR
Maximum Segment Size Register.
Definition: W5100.hh:220
Mask PPPoE Connection Close.
Definition: W5100.hh:187
uint8_t IR
Interrupt Register.
Definition: W5100.hh:143
uint8_t TMSR
TX Memory Size Register.
Definition: W5100.hh:148
uint16_t TX_FSR
TX Free Size Register.
Definition: W5100.hh:225
uint16_t TX_RD
TX Read Pointer Register.
Definition: W5100.hh:226
uint16_t TX_WR
TX Write Pointer Register.
Definition: W5100.hh:227
void write(uint16_t addr, uint8_t data)
Definition: W5100.hh:622
Socket 0 memory size position.
Definition: W5100.hh:201
uint16_t m_tx_len
Definition: W5100.hh:509
static const uint8_t MAC[6]
Definition: W5100.hh:593
Occurrence of Socket 2 Interrupt.
Definition: W5100.hh:176
uint16_t RX_RD
RX Read Pointer Register.
Definition: W5100.hh:229
const uint8_t * m_mac
Definition: W5100.hh:606
uint8_t SHAR[6]
Source Hardware Address Register.
Definition: W5100.hh:140
CommonRegister * m_creg
Definition: W5100.hh:600
bool begin(uint8_t ip[4]=NULL, uint8_t subnet[4]=NULL, uint16_t timeout=500)
Definition: W5100.cpp:75
W5100 * m_dev
Definition: W5100.hh:500
Socket * socket(Socket::Protocol proto, uint16_t port=0, uint8_t flag=0)
Flag mask.
Definition: W5100.hh:238
Address Auto-Increment.
Definition: W5100.hh:164
UDP: Transmit data.
Definition: W5100.hh:262
uint8_t MR
Mode Register.
Definition: W5100.hh:212
PPPoE Mode.
Definition: W5100.hh:163
const class prog_str * str_P
Definition: Types.h:187
static const uint8_t TX_MEMORY_SIZE
Definition: W5100.hh:315
static const uint16_t TX_MEMORY_BASE
Definition: W5100.hh:305
Receiving packet to RX_RD.
Definition: W5100.hh:264
Destination unreachable.
Definition: W5100.hh:173
uint16_t RX_RSR
RX Received Size Register.
Definition: W5100.hh:228
Occurrence of Socket 3 Interrupt.
Definition: W5100.hh:175
void issue(uint16_t addr, uint8_t cmd)
TCP: Disconnect server/client.
Definition: W5100.hh:259
Mask IP Conflict.
Definition: W5100.hh:185
IOStream & flush(IOStream &outs)
Definition: IOStream.hh:853
Connection established.
Definition: W5100.hh:275
int bind(uint8_t ip[4], uint8_t subnet[4], uint8_t gateway[4]=NULL)
IP Conflict.
Definition: W5100.hh:172
uint8_t PROTO
Protocol in IP Raw mode.
Definition: W5100.hh:221
uint8_t CR
Command Register.
Definition: W5100.hh:213
uint8_t PATR[2]
Authentication Type in PPPoE.
Definition: W5100.hh:149
static const uint8_t SOCK_MAX
Definition: W5100.hh:322
uint16_t m_tx_buf
Definition: W5100.hh:503
uint16_t m_local
Definition: W5100.hh:603
Close socket.
Definition: W5100.hh:260
PPPoE Connection Close.
Definition: W5100.hh:174
static const uint16_t TX_MEMORY_MAX
Definition: W5100.hh:306
void write_P(uint16_t addr, const void *buf, size_t len)
Definition: W5100.hh:643
S/W Reset.
Definition: W5100.hh:161
Use No Delay ACK.
Definition: W5100.hh:241
uint8_t TOS
IP TOS.
Definition: W5100.hh:222
Mask Destination unreachable.
Definition: W5100.hh:186
static const uint8_t DNS_RETRY_MAX
Definition: W5100.hh:325
Timeout occured.
Definition: W5100.hh:272
Connection termination.
Definition: W5100.hh:274
static const uint16_t BUF_MASK
Definition: W5100.hh:314
Mask occurrence of Socket 2 Interrupt.
Definition: W5100.hh:189
Socket 3 memory size position.
Definition: W5100.hh:198
static const uint16_t RX_MEMORY_BASE
Definition: W5100.hh:309
Mask occurrence of Socket 1 Interrupt.
Definition: W5100.hh:190
uint8_t IR
Interrupt Register.
Definition: W5100.hh:214
static const uint16_t RX_MEMORY_MAX
Definition: W5100.hh:310
bool end()
TCP: Check connection status.
Definition: W5100.hh:263
W5100(const uint8_t *mac=NULL, Board::DigitalPin csn=Board::D10)
Indirect Bus I/F mode.
Definition: W5100.hh:165
bool begin_P(const char *hostname, uint16_t timeout=500)
Occurrence of Socket 1 Interrupt.
Definition: W5100.hh:177
Mask occurrence of Socket 0 Interrupt.
Definition: W5100.hh:191
Ping Block Mode.
Definition: W5100.hh:162
Driver m_sock[SOCK_MAX]
Definition: W5100.hh:597
TCP: Initiate server mode.
Definition: W5100.hh:257
Initiate socket according to MR.
Definition: W5100.hh:256
uint8_t PMAGIC
PPP LCP Magic number.
Definition: W5100.hh:152
Received data.
Definition: W5100.hh:273